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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. TPS65263-1Q1 slvsdy9 ? march 2017 TPS65263-1Q1 4.0- to 18-v input voltage, 3-a/2-a/2-a output current triple synchronous step-down converter with i 2 c controlled dynamic voltage scaling 1 1 features 1 ? qualified for automotive applications ? aec-q100 qualification with the following results: ? device temperature grade 1: ? 40 c to 125 c operating junction temperature range ? device hbm esd classification level h2 ? device cdm esd classification level c4b ? operating input voltage range 4.0- to 18-v maximum continuous output current 3 a/2 a/2 a ? i 2 c controlled 7-bits vid programmable output voltage from 0.68 to 1.95 v with 10-mv voltage step for buck2 ? i 2 c controlled vid voltage transition slew rate for buck2 ? i 2 c read back power good status, overcurrent warning and die temperature warning ? i 2 c compatible interface with standard mode (100 khz) and fast mode (400 khz) ? feedback reference voltage 0.6 v 1% ? adjustable clock frequency from 200 khz to 2.3 mhz ? fcc mode (default) ? external clock synchronization ? dedicated enable and soft-start pins for each buck ? output voltage power good indicator ? thermal overloading protection 2 applications ? automotive ? car audio/video ? home gateway and access point networks ? surveillance 3 description the TPS65263-1Q1 incorporates triple-synchronous buck converters with 4.0- to 18-v wide input voltage. the converter with constant frequency peak current mode is designed to simplify its application while giving designers options to optimize the system according to targeted applications. the switching frequency of the converters is adjustable from 200 khz to 2.3 mhz with an external resistor. 180 out-of- phase operation between buck1 and buck2, buck3 (buck2 and buck3 run in phase) minimizes the input filter requirements. the initial startup voltage of each buck can be set with external feedback resistors. the output voltage of buck2 can be dynamically scaled from 0.68 to 1.95 v in 10-mv steps with i 2 c-controlled 7 bits vid. the vid voltage transition slew rate is programmable with 3-bits control through i 2 c bus to optimize overshoot/undershoot during vid voltage transition. each buck in TPS65263-1Q1 can be i 2 c controlled for enabling/disabling output voltage, setting the pulse skipping mode (psm) or forced continuous current (fcc) mode at light load condition and reading the power-good status, overcurrent warning, and die temperature warning. the TPS65263-1Q1 features overvoltage, overcurrent, short-circuit, and overtemperature protection. device information (1) part number package body size (nom) TPS65263-1Q1 vqfn (32) 5.00 mm 5.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. application schematic efficiency vs output load lx1 fb1 lx2 fb2 lx3 fb3 pvinx vin enx ssx sda scl pgnd agnd vin vout1 vout3 TPS65263-1Q1 vout2 dvcc sda scl pgood rosc vout2 vout2 copyright ? 2017, texas instruments incorporated output load (a) efficiency (%) 0.01 0.1 1 2 0 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% d022 4 v in vout = 1.5 v 5 v in vout = 1.5 v productfolder ordernow technical documents tools & software referencedesign support &community
2 TPS65263-1Q1 slvsdy9 ? march 2017 www.ti.com product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 5 6.1 absolute maximum ratings ...................................... 5 6.2 esd ratings .............................................................. 5 6.3 recommended operating conditions ....................... 5 6.4 thermal information .................................................. 5 6.5 electrical characteristics ........................................... 6 6.6 typical characteristics .............................................. 8 7 detailed description ............................................ 12 7.1 overview ................................................................. 12 7.2 functional block diagram ....................................... 13 7.3 feature description ................................................. 13 7.4 device functional modes ........................................ 24 7.5 register maps ........................................................ 26 8 application and implementation ........................ 29 8.1 application information ............................................ 29 8.2 typical application ................................................. 29 9 power supply recommendations ...................... 37 10 layout ................................................................... 37 10.1 layout guidelines ................................................. 37 10.2 layout example .................................................... 38 11 device and documentation support ................. 39 11.1 receiving notification of documentation updates 39 11.2 community resources .......................................... 39 11.3 trademarks ........................................................... 39 11.4 electrostatic discharge caution ............................ 39 11.5 glossary ................................................................ 39 12 mechanical, packaging, and orderable information ........................................................... 39 4 revision history date revision notes march 2017 * initial release.
3 TPS65263-1Q1 www.ti.com slvsdy9 ? march 2017 product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 5 pin configuration and functions rhb package 32-pin vqfn top view there is no electric signal down bonded to thermal pad inside ic. exposed thermal pad must be soldered to pcb for optimal thermal performance. pin functions pin description name no. en3 1 enable for buck3. float to enable. can use this pin to adjust the input uvlo of buck3 with a resistor divider. sda 2 i 2 c interface data pin; float or connect to gnd to disable i 2 c communication scl 3 i 2 c interface clock pin; float or connect to gnd to disable i 2 c communication agnd 4 analog ground common to buck controllers and other analog circuits. it must be routed separately from high-current power grounds to the ( ? ) terminal of bypass capacitor of input voltage vin. vout2 5 buck2 output voltage sense pin fb2 6 feedback kelvin sensing pin for buck2 output voltage. connect this pin to buck2 resistor divider. comp2 7 error amplifier output and loop compensation pin for buck2. connect a series resistor and capacitor to compensate the control loop of buck2 with peak current pwm mode. ss2 8 soft-start and tracking input for buck2. an internal 5.2- a pullup current source is connected to this pin. the soft-start time can be programmed by connecting a capacitor between this pin and ground. bst2 9 boot-strapped supply to the high-side floating gate driver in buck2. connect a capacitor (recommend 47 nf) from bst2 pin to lx2 pin. lx2 10 switching node connection to the inductor and bootstrap capacitor for buck2. the voltage swing at this pin is from a diode voltage below the ground up to pvin2 voltage. pgnd2 11 power ground connection of buck2. connect pgnd2 pin as close as practical to the ( ? ) terminal of vin2 input ceramic capacitor. pvin2 12 input power supply for buck2. connect pvin2 pin as close as practical to the (+) terminal of an input ceramic capacitor (suggest 10 f). pvin3 13 input power supply for buck3. connect pvin3 pin as close as practical to the (+) terminal of an input ceramic capacitor (suggest 10 f). pgnd3 14 power ground connection of buck3. connect pgnd3 pin as close as practical to the ( ? ) terminal of vin3 input ceramic capacitor. 1 2 3 4 5 6 9 1 0 1 1 1 2 1 3 1 4 2 4 2 3 2 2 2 1 2 0 1 9 3 2 3 1 3 0 2 9 2 8 2 7 bst1 pgnd1 lx1 vin vout2 agnd fb1 v7v pvin1 bst2 lx2 pvin2 pvin3 lx3 thermal pad 1 5 2 6 7 1 8 8 comp2 bst3 1 6 comp3 1 7 2 5 pgood fb3 sda en1 en3 scl ss1 ss3 ss2 fb2 rosc pgnd3 pgnd2 comp1 en2
4 TPS65263-1Q1 slvsdy9 ? march 2017 www.ti.com product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated pin functions (continued) pin description name no. lx3 15 switching node connection to the inductor and bootstrap capacitor for buck3. the voltage swing at this pin is from a diode voltage below the ground up to pvin3 voltage. bst3 16 boot-strapped supply to the high-side floating gate driver in buck3. connect a capacitor (recommend 47 nf) from bst3 pin to lx3 pin. ss3 17 soft-start and tracking input for buck3. an internal 5.2- a pullup current source is connected to this pin. the soft-start time can be programmed by connecting a capacitor between this pin and ground. comp3 18 error amplifier output and loop compensation pin for buck3. connect a series resistor and capacitor to compensate the control loop of buck3 with peak current pwm mode. fb3 19 feedback kelvin sensing pin for buck3 output voltage. connect this pin to buck3 resistor divider. pgood 20 output voltage supervision pin. when all bucks are in pgood monitor ? s regulation range, pgood is asserted high. rosc 21 clock frequency adjustment pin. connect a resistor from this pin to ground to adjust the clock frequency. when connected to an external clock, the internal oscillator synchronizes to the external clock. fb1 22 feedback kelvin sensing pin for buck1 output voltage. connect this pin to buck1 resistor divider. comp1 23 error amplifier output and loop compensation pin for buck1. connect a series resistor and capacitor to compensate the control loop of buck1 with peak current pwm mode. ss1 24 soft-start and tracking input for buck1. an internal 5.2- a pullup current source is connected to this pin. the soft-start time can be programmed by connecting a capacitor between this pin and ground. bst1 25 boot-strapped supply to the high-side floating gate driver in buck1. connect a capacitor (recommend 47 nf) from bst1 pin to lx1 pin. lx1 26 switching node connection to the inductor and bootstrap capacitor for buck1. the voltage swing at this pin is from a diode voltage below the ground up to pvin1 voltage. pgnd1 27 power ground connection of buck1. connect pgnd1 pin as close as practical to the ( ? ) terminal of vin1 input ceramic capacitor. pvin1 28 input power supply for buck1. connect pvin1 pin as close as practical to the (+) terminal of an input ceramic capacitor (suggest 10 f). vin 29 buck controller power supply v7v 30 internal ldo for gate driver and internal controller. connect a 1- f capacitor from the pin to power ground. en1 31 enable for buck1. float to enable. can use this pin to adjust the input uvlo of buck1 with a resistor divider. en2 32 enable for buck2. float to enable. can use this pin to adjust the input uvlo of buck2 with a resistor divider. pad ? there is no electric signal down bonded to thermal pad inside ic. exposed thermal pad must be soldered to pcb for optimal thermal performance.
5 TPS65263-1Q1 www.ti.com slvsdy9 ? march 2017 product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature (unless otherwise noted) (1) min max unit pvin1, pvin2, pvin3,vin ? 0.3 20 v lx1, lx2, lx3 (maximum withstand voltage transient < 20 ns) ? 1.0 20 v bst1, bst2, bst3 referenced to lx1, lx2, lx3 pins respectively ? 0.3 7 v en1, en2, en3, v7v, vout2, scl, sda, pgood ? 0.3 7 v fb1, fb2, fb3, comp1 , comp2, comp3, rosc, ss1, ss2, ss3 ? 0.3 3.6 v agnd, pgnd1, pgnd2, pgnd3 ? 0.3 0.3 v t j operating junction temperature ? 40 150 c t stg storage temperature ? 55 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001, all -2000 2000 pins (1) 2000 v charged device model (cdm), per jedec specification jesd22-c101, all pins (2) 500 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min max unit pvin1, pvin2, pvin3,vin 4 18 v lx1, lx2, lx3 (maximum withstand voltage transient < 20 ns) ? 0.8 18 v bst1, bst2, bst3 referenced to lx1, lx2, lx3 pins respectively ? 0.1 6.8 v en1, en2, en3, v7v, vout1, vout2, vout3, scl, sda ? 0.1 6.3 v fb1, fb2, fb3, comp1 , comp2, comp3, ss1, ss2, ss3 ? 0.1 3 v t j operating junction temperature ? 40 125 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . 6.4 thermal information thermal metric (1) TPS65263-1Q1 unit rhb (vqfn) 32 pins r ja junction-to-ambient thermal resistance 33.3 c/w r jc(top) junction-to-case (top) thermal resistance 25.7 c/w r jb junction-to-board thermal resistance 7.4 c/w jt junction-to-top characterization parameter 0.3 c/w jb junction-to-board characterization parameter 7.3 c/w r jc(bot) junction-to-case (bottom) thermal resistance 2.1 c/w
6 TPS65263-1Q1 slvsdy9 ? march 2017 www.ti.com product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated (1) lab validation result 6.5 electrical characteristics v in = 12 v, f sw = 500 khz, t j = ? 40 c to 125 c, typical values are at t j = 25 c (unless otherwise noted) parameter test conditions min typ max unit input supply voltage vin input voltage range 4 18 v uvlo vin uvlo vin rising 3.5 3.8 4 v vin falling 3.1 3.3 3.5 v hysteresis 500 mv idd sdn shutdown supply current en1 = en2 = en3 = 0 v 4 9.5 18 a idd q_nsw input quiescent current without buck1/2/3 switching en1 = en2 = en3 = 5 v, fb1 = fb2 = fb3 = 0.8 v 550 780 1150 a idd q_nsw1 en1 = 5 v, en2 = en3 = 0 v, fb1 = 0.8 v 180 370 590 a idd q_nsw2 en2 = 5 v, en1 = en3 = 0 v, fb2 = 0.8v 180 370 590 a idd q_nsw3 en3 = 5 v, en1 = en2 = 0 v, fb3 = 0.8 v 180 370 590 a v 7v v7v ldo output voltage v 7v load current = 0 a 6.3 v i ocp_v7v v7v ldo current limit 78 185 260 ma feedback voltage reference v fb feedback voltage v comp = 1.2 v 0.594 0.6 0.606 v buck1, buck2, buck3 v enxh en1/2/3 high-level input voltage 1.12 1.2 1.26 v v enxl en1/2/3 low-level input voltage 1.05 1.15 1.21 v i enx1 en1/2/3 pullup current enx = 1 v 2.5 3.9 5.9 a i enx2 en1/2/3 pullup current enx = 1.5 v 5.1 6.9 9.2 a i enhys hysteresis current 2.6 3 3.3 a i ssx soft-start charging current 3.9 5.2 6.5 a t on_min minimum on-time 50 75 110 ns g m_ea error amplifier transconductance ? 2 a < i compx < 2 a 140 300 450 s g m_ps1/2/3 comp1/2/3 voltage to inductor current g m (1) i lx = 0.5 a 7.4 a/v i limit1 buck1 peak inductor current limit 4.3 5.4 6.5 a i limitsink1 buck1 low-side sink current limit 0.7 1.3 1.8 a i limit2/3 buck2/buck3 peak inductor current limit 2.55 3.3 3.9 a i limitsink2/3 buck2/buck3 low-side sink current limit 0.5 1 1.4 a rdson_hs1 buck1 high-side switch resistance vin = 12 v 105 m rdson_ls1 buck1 low-side switch resistance vin = 12 v 65 m rdson_hs2 buck2 high-side switch resistance vin = 12 v 140 m rdson_ls2 buck2 low-side switch resistance vin = 12 v 90 m rdson_hs3 buck3 high-side switch resistance vin = 12 v 140 m rdson_ls3 buck3 low-side switch resistance vin = 12 v 90 m hiccup timing t hiccup_wait overcurrent wait time (1) 256 cycles t hiccup_re hiccup time before restart (1) 8192 cycles power good v th_pg feedback voltage threshold fbx undervoltage falling 92.5 %v ref fbx undervoltage rising 95 fbx overvoltage rising 107.5 fbx overvoltage falling 105 t deglitch(pg)_f pgood falling edge deglitch time 112 cycles t rdeglitch(pg)_r pgood rising edge deglitch time 616 cycles i pg pgood pin leakage 0.1 a v low_pg pgood pin low voltage i sink = 1 ma 0.4 v
7 TPS65263-1Q1 www.ti.com slvsdy9 ? march 2017 product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated electrical characteristics (continued) v in = 12 v, f sw = 500 khz, t j = ? 40 c to 125 c, typical values are at t j = 25 c (unless otherwise noted) parameter test conditions min typ max unit (2) not production tested oscillator f sw switching frequency r osc = 88.7 k 430 500 560 khz f sw_range switching frequency 200 2300 khz t sync_w clock sync minimum pulse width 80 ns f sync_hi clock sync high threshold 2 v v sync_lo clock sync low threshold 0.4 v f sync clock sync frequency range 200 2300 khz thermal protection t trip_otp thermal protection trip point (1) temperature rising 160 c t hyst_otp hysteresis 20 c i 2 c interface addr address (2) 0x60h v ih sda,scl input high voltage 2 v v il sda,scl input low voltage 0.4 v i i input current sda, scl, vi = 0.4 to 4.5 v ? 10 10 a vol sda sda output low voltage sda open drain, i ol = 4 ma 0.4 v ? (scl) maximum scl clock frequency (2) 400 khz t buf bus free time between a stop and start condition (2) 1.3 s t hd_sta hold time (repeated) start condition (2) 0.6 s t su_sto setup time for stop condition (2) 0.6 s t low low period of the scl clock (2) 1.3 s t high high period of the scl clock (2) 0.6 s t su_sta setup time for a repeated start condition (2) 0.6 s t su_dat data setup time (2) 0.1 s t hd_dat data hold time (2) 0 0.9 s t rcl rise time of scl signal (2) capacitance of one bus line (pf) 20 + 0.1cb 300 ns t rcl1 rise time of scl signal after a repeated start condition and after an acknowledge bit (2) capacitance of one bus line (pf) 20 + 0.1cb 300 ns t fcl fall time of scl signal (2) capacitance of one bus line (pf) 20 + 0.1cb 300 ns t rda rise time of sda signal (2) capacitance of one bus line (pf) 20 + 0.1cb 300 ns t fda fall time of sda signal (2) capacitance of one bus line (pf) 20 + 0.1cb 300 ns c b capacitance of bus line(scl and sda) (2) 400 pf
8 TPS65263-1Q1 slvsdy9 ? march 2017 www.ti.com product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 6.6 typical characteristics t a = 25 c, vin = 12 v, v out1 = 1.5 v, v out2 = 1.2 v, v out3 = 2.5 v, f sw = 500 khz (unless otherwise noted) figure 1. buck1 efficiency figure 2. buck2 efficiency figure 3. buck3 efficiency figure 4. buck1, load regulation figure 5. buck2, load regulation figure 6. buck3, load regulation output load (a) output voltage (v) 0 0.5 1 1.5 2 2.485 2.49 2.495 2.5 2.505 2.51 2.515 2.52 2.525 d006 5 v in 12 v in output load (a) efficiency (%) 0.01 0.1 1 2 0 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% d003 5 v in 12 v in output load (a) output voltage (v) 0 0.5 1 1.5 2 2.5 3 1.475 1.48 1.485 1.49 1.495 1.5 1.505 1.51 1.515 d004 5 v in 12 vi n output load (a) efficiency (%) 0.01 0.1 1 2 0 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% d002 5 v in 12 v in output load (a) output voltage (v) 0 0.5 1 1.5 2 1.18 1.185 1.19 1.195 1.2 1.205 1.21 1.215 1.22 d005 5 v in 12 v in
9 TPS65263-1Q1 www.ti.com slvsdy9 ? march 2017 product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) t a = 25 c, vin = 12 v, v out1 = 1.5 v, v out2 = 1.2 v, v out3 = 2.5 v, f sw = 500 khz (unless otherwise noted) figure 7. buck1, line regulation figure 8. buck2, line regulation figure 9. buck3, line regulation figure 10. voltage reference vs temperature rosc = 88.7 k figure 11. oscillator frequency vs temperature v in = 12 v figure 12. shutdown quiescent current vs temperature junction temperature ( q c) oscillator frequency (khz) -50 -30 -10 10 30 50 70 90 110 130 460 480 500 520 540 d011 junction temperature ( q c) shutdown quiescent current (ua) -50 -30 -10 10 30 50 70 90 110 130 5 7 9 11 13 15 d012 input voltage (v) output voltage (v) 4 6 8 10 12 14 16 18 2.495 2.5 2.505 2.51 2.515 d009 i out = 0 a i out = 1 a i out = 2 a junction temperature ( q c) voltage reference (v) -50 -30 -10 10 30 50 70 90 110 130 0.594 0.596 0.598 0.6 0.602 0.604 0.606 d010 input voltage (v) output voltage (v) 4 6 8 10 12 14 16 18 1.48 1.485 1.49 1.495 1.5 1.505 1.51 d007 i out = 0 a i out = 1 a i out = 3 a input voltage (v) output voltage (v) 4 6 8 10 12 14 16 18 1.19 1.195 1.2 1.205 1.21 d008 i out = 0 a i out = 1 a i out = 2 a
10 TPS65263-1Q1 slvsdy9 ? march 2017 www.ti.com product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) t a = 25 c, vin = 12 v, v out1 = 1.5 v, v out2 = 1.2 v, v out3 = 2.5 v, f sw = 500 khz (unless otherwise noted) en = 1 v v in = 12 v figure 13. en pin pullup current vs temperature, en = 1.0 v en = 1.5 v v in = 12 v figure 14. en pin pullup current vs temperature, en = 1.5 v v in = 12 v figure 15. en pin threshold rising vs temperature v in = 12 v figure 16. en pin threshold falling vs temperature v in = 12 v figure 17. ss pin charge current vs temperature v in = 12 v figure 18. buck1 high-side current limit vs temperature junction temperature ( q c) high side current limit (a) -50 -30 -10 10 30 50 70 90 110 130 5 5.2 5.4 5.6 5.8 d018 junction temperature ( q c) pin threshold raising (v) -50 -30 -10 10 30 50 70 90 110 130 1.12 1.16 1.2 1.24 1.28 d015 junction temperature ( q c) pin threshold falling (v) -50 -30 -10 10 30 50 70 90 110 130 1.07 1.11 1.15 1.19 1.23 d016 junction temperature ( q c) en pin on pullup (ua) -50 -30 -10 10 30 50 70 90 110 130 3 3.4 3.8 4.2 4.6 5 d013 junction temperature ( q c) en pin on pullup (ua) -50 -30 -10 10 30 50 70 90 110 130 6 6.4 6.8 7.2 7.6 8 d014 junction temperature ( q c) soft start current (ma) -50 -30 -10 10 30 50 70 90 110 130 4.6 4.8 5 5.2 5.4 5.6 d017
11 TPS65263-1Q1 www.ti.com slvsdy9 ? march 2017 product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated typical characteristics (continued) t a = 25 c, vin = 12 v, v out1 = 1.5 v, v out2 = 1.2 v, v out3 = 2.5 v, f sw = 500 khz (unless otherwise noted) v in = 12 v figure 19. buck2 high-side current limit vs temperature v in = 12 v figure 20. buck3 high-side current limit vs temperature junction temperature ( q c) high side current limit (a) -50 -30 -10 10 30 50 70 90 110 130 2.8 3 3.2 3.4 3.6 3.8 d019 junction temperature ( q c) high side current limit (a) -50 -30 -10 10 30 50 70 90 110 130 2.8 3 3.2 3.4 3.6 3.8 d020
12 TPS65263-1Q1 slvsdy9 ? march 2017 www.ti.com product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7 detailed description 7.1 overview the TPS65263-1Q1 is a monolithic, triple-synchronous step-down (buck) converter with 3-a/2-a/2-a output currents. a wide 4- to 18-v input supply voltage range encompasses most intermediate bus voltages operating off 5-, 9-, 12-, or 15-v power bus. the feedback voltage reference for each buck is 0.6 v. each buck is independent with dedicated enable, soft-start, and loop compensation pins. the TPS65263-1Q1 is equipped with an i 2 c compatible bus for communication with soc to control buck converters. through the i 2 c interface, soc can enable or disable the buck converters, set output voltage (buck2 only), and read status registers. external feedback divider resistors can set the initial start-up voltage of the buck2. after the voltage identification vid dac is updated via the i 2 c, output voltage of the buck2 can be independently programmed with 7 bits vid from 0.68 to 1.95 v in 10-mv voltage step resolution. output voltage of the buck2 transition begins after the i 2 c interface receives the command for the go bit in the command register. if sda and scl pins are floated or are connected to gnd, the i 2 c communication will be rejected and the TPS65263-1Q1 will operate as a traditional triple buck. each buck on or off is separately controlled by the relevant enable pin. buck2 ? s output voltage is set with the external feedback divider resistors. in the light load condition, the converter operates at continuous current mode (ccm) with a fixed frequency for optimized output ripple. psm can be enabled through i2c so that the converter automatically operates in pulse skipping mode (psm) to save power. the TPS65263-1Q1 implements a constant frequency, peak current mode control that simplifies external loop compensation. the wide switching frequency of 200 khz to 2.3 mhz allows for optimizing system efficiency, filtering size, and bandwidth. the switching frequency can be adjusted with an external resistor connecting between the rosc pin and ground. the TPS65263-1Q1 also has an internal phase locked loop (pll) controlled by the rosc pin that can be used to synchronize the switching cycle to the falling edge of an external system clock. the switching clock of buck1 is 180 out-of-phase operation from the clocks of buck2 and buck3 channels to reduce input current ripple, input capacitor size, and power-supply-induced noise. the TPS65263-1Q1 is designed for safe monotonic startup into prebiased loads. the default startup is when vin is typically 3.8 v. the enx pin can also be used to adjust the input voltage undervoltage lockout (uvlo) with an external resistor divider. in addition, the enx pin has an internal 3.9- a current source, so the en pin can be floating for automatically powering up the converters. the TPS65263-1Q1 reduces the external component count by integrating the bootstrap circuit. the bias voltage for the integrated high-side mosfet is supplied by a capacitor between the bst and lx pins. a uvlo circuit monitors the bootstrap capacitor voltage v bst -v lx in each buck. when v bst -v lx voltage drops to the threshold, lx pin is pulled low to recharge the bootstrap capacitor. the TPS65263-1Q1 can operate at 100% duty cycle as long as the bootstrap capacitor voltage is higher than the boot-lx uvlo threshold, which is typically 2.1 v. the TPS65263-1Q1 has power-good comparators with hysteresis, which monitor the output voltages through internal feedback voltages. i 2 c can read the power-good status with the command register. the device also features the pgood pin to supervise output voltages of the buck converter. when all bucks are in regulation range and power sequence is done, pgood is asserted high. the ss (soft-start/tracking) pin is used to minimize inrush currents or provide power-supply sequencing during power up. a small value capacitor or resistor divider is connected to the pin for soft start or voltage tracking. the TPS65263-1Q1 is protected from overload and overtemperature fault conditions. the converter minimizes excessive output overvoltage transients by taking advantage of the power-good comparator. when the output is over, the high-side mosfet is turned off until the internal feedback voltage is lower than 105% of the 0.6-v reference voltage. the TPS65263-1Q1 implements both high-side mosfet overload protection and bidirectional low-side mosfet overload protections to avoid inductor current runaway. if the overcurrent condition has lasted for more than the oc wait time (256 clock cycle), the converter shuts down and restarts after the hiccup time (8192 clock cycles). the TPS65263-1Q1 shuts down if the junction temperature is higher than thermal shutdown trip point. when the junction temperature drops 20 c typically below the thermal shutdown trip point, the TPS65263-1Q1 is restarted under control of the soft-start circuit automatically.
13 TPS65263-1Q1 www.ti.com slvsdy9 ? march 2017 product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.2 functional block diagram 7.3 feature description 7.3.1 adjusting the output voltage the output voltage of each buck is set with a resistor divider from the output of buck to the fb pin. ti recommends to use 1% tolerance or better resistors. pvin1 buck1 enable vfb comp clk v7v vin bst lx pgnd bst1 lx1 pgnd1 pvin2 bst2 lx2 pgnd2 buck2 enable comp vfb clk v7v vin bst lx pgnd i 2 c sda scl clk/sync/ phase shift v7v ldo bias v7v ien_buck1 comp1 fb2 comp2 fb1 clk1 clk2 vin en_buck1 en_buck2 7 over temp vfb2 vfb1 agnd vfb1 vfb2 dvcc i 2 c bus vin 29 30 2 3 4 7 11 10 9 12 22 27 26 25 28 power good ot warning pgood en_buck1 en_buck2 ss 24 ss 8 v7v 5 6 mux vout2 7-bit i 2 c reg. i 2 c reg. en2 en3 ss1 23 ss2 pvin3 buck3 enable vfb comp clk v7v vin bst lx pgnd bst3 lx3 pgnd3 comp3 fb3 en_buck3 vfb3 19 14 15 16 13 ss 17 v7v ss3 18 clk3 vfb3 en1 en_buck3 en1 en2 en3 3 ua 1.2 v 3.9 ua 2 k 6.3 v 3 ua 1.2 v 3.9 ua 6.3 v 3 ua 1.2 v 3.9 ua 6.3 v 2 k 2 k 31 32 1 vin vin ien_buck1 ien_buck2 ien_buck3 pgood rosc 21 20 ien_buck2 ien_buck3 vin copyright ? 2017, texas instruments incorporated
14 TPS65263-1Q1 slvsdy9 ? march 2017 www.ti.com product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated feature description (continued) figure 21. voltage divider circuit (1) to improve efficiency at light loads consider using larger value resistors. if the values are too high, the regulator is more sensitive to noise. table 1 shows the recommended resistor values. table 1. output resistor divider selection output voltage (v) r1 (k ) r2 (k ) 1 10 15 1.2 10 10 1.5 15 10 1.8 20 10 2.5 31.6 10 3.3 45.3 10 3.3 22.6 4.99 5 73.2 10 5 36.5 4.99 the output voltage of the buck converter can be dynamically scaled by i 2 c-controlled 7-bit register, voutx_sel. before i 2 c communication, the output voltage is set with the resistor divider from the output of buck to the fb pin. when the go bit is set to 1 through the i 2 c interface, the buck converter switches the external resistor divider to the internal resistor divider as shown in figure 22 . the output voltage can be selected among 128 voltages with voltage identifications (vid) shown in table 2 . the output voltage range of dynamic voltage scaling is 0.68 to 1.95 v with 10-mv resolution of each voltage step. figure 22. voltage divider circuit vout2 fb2 r1 r2 0.6 v comp2 01 r1 r2 agnd vout2 vout _ sel<7> 3*2%lw vout _ sel<0:6> 150 k 7.5 k ~ 207 k 2 1 out 0.6 r r v 0.6 = - vout fb r1 r2 0.6 v comp
15 TPS65263-1Q1 www.ti.com slvsdy9 ? march 2017 product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated table 2. v out output voltage setting out_sel < 7:0 > v out (v) vout_sel < 7:0 > v out (v) vout_sel < 7:0 > v out (v) vout_sel < 7:0 > v out (v) 0 0.68 20 1 40 1.32 60 1.64 1 0.69 21 1.01 41 1.33 61 1.65 2 0.7 22 1.02 42 1.34 62 1.66 3 0.71 23 1.03 43 1.35 63 1.67 4 0.72 24 1.04 44 1.36 64 1.68 5 0.73 25 1.05 45 1.37 65 1.69 6 0.74 26 1.06 46 1.38 66 1.7 7 0.75 27 1.07 47 1.39 67 1.71 8 0.76 28 1.08 48 1.4 68 1.72 9 0.77 29 1.09 49 1.41 69 1.73 a 0.78 2a 1.1 4a 1.42 6a 1.74 b 0.79 2b 1.11 4b 1.43 6b 1.75 c 0.8 2c 1.12 4c 1.44 6c 1.76 d 0.81 2d 1.13 4d 1.45 6d 1.77 e 0.82 2e 1.14 4e 1.46 6e 1.78 f 0.83 2f 1.15 4f 1.47 6f 1.79 10 0.84 30 1.16 50 1.48 70 1.8 11 0.85 31 1.17 51 1.49 71 1.81 12 0.86 32 1.18 52 1.5 72 1.82 13 0.87 33 1.19 53 1.51 73 1.83 14 0.88 34 1.2 54 1.52 74 1.84 15 0.89 35 1.21 55 1.53 75 1.85 16 0.9 36 1.22 56 1.54 76 1.86 17 0.91 37 1.23 57 1.55 77 1.87 18 0.92 38 1.24 58 1.56 78 1.88 19 0.93 39 1.25 59 1.57 79 1.89 1a 0.94 3a 1.26 5a 1.58 7a 1.9 1b 0.95 3b 1.27 5b 1.59 7b 1.91 1c 0.96 3c 1.28 5c 1.6 7c 1.92 1d 0.97 3d 1.29 5d 1.61 7d 1.93 1e 0.98 3e 1.3 5e 1.62 7e 1.94 1f 0.99 3f 1.31 5f 1.63 7f 1.95 7.3.2 enable and adjusting uvlo the enx pin provides electrical on and off control of the device. after the enx pin voltage exceeds the threshold voltage, the device starts operation. if each enx pin voltage is pulled below the threshold voltage, the regulator stops switching and enters a low iq state. the en pin has an internal pullup current source, allowing the user to float the en pin for enabling the device. if an application requires controlling the en pin, use open-drain or open-collector output logic to interface with the pin. the device implements internal uvlo circuitry on the vin pin. the device is disabled when the vin pin voltage falls below the internal vin uvlo threshold. the internal vin uvlo threshold has a hysteresis of 500 mv. if an application requires either a higher uvlo threshold on the vin pin or a secondary uvlo on the pvinx in split rail applications, then the user can configure the enx pin as shown in figure 23 , figure 24 , and figure 25 . when using the external uvlo function, ti recommends to set the hysteresis > 500 mv.
16 TPS65263-1Q1 slvsdy9 ? march 2017 www.ti.com product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated the en pin has a small pullup current, i p , which sets the default state of the pin to enable when no external components are connected. the pullup current is also used to control the voltage hysteresis for the uvlo function because it increases by i h after the en pin crosses the enable threshold. the uvlo thresholds can be calculated using equation 2 and equation 3 . (2) where ? i h = 3 a ? i p = 3.9 a ? v enrising = 1.2 v ? v enfalling = 1.15 v (3) figure 23. adjustable vin uvlo figure 24. adjustable pvin uvlo, vin > 4 v figure 25. adjustable vin and pvin uvlo vin r1 r2 en i h i p pvin vin r1 r2 en i h i p pvin r1 r2 en i h i p ( ) 1 enfalling 2 stop enfalling 1 h p r v r v v r i i = - + + enfalling start stop enrising 1 enfalling p h enrising v v v v r v i 1 i v ? ? - ? ? = ? ? - + ? ?
17 TPS65263-1Q1 www.ti.com slvsdy9 ? march 2017 product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.3.3 soft-start time the voltage on the respective ss pin controls the startup of buck output. when the voltage on the ss pin is less than the internal 0.6-v reference, the TPS65263-1Q1 regulates the internal feedback voltage to the voltage on the ss pin instead of 0.6 v. the ss pin can be used to program an external soft-start function or to allow output of buck to track another supply during start-up. the device has an internal pullup current source of 5.2 a (typical) that charges an external soft-start capacitor to provide a linear ramping voltage at the ss pin. the TPS65263-1Q1 regulates the internal feedback voltage to the voltage on the ss pin, allowing vout to rise smoothly from 0 v to its regulated voltage without inrush current. the soft-start time can be calculated approximately by equation 4 . (4) many of the common power-supply sequencing methods can be implemented using the ssx and enx pins. figure 26 shows the method implementing ratiometric sequencing by connecting the ssx pins of three buck channels together. the regulator outputs ramp up and reach regulation at the same time. when calculating the soft-start time, the pullup current source must be tripled in equation 4 . figure 26. ratiometric power-up using ssx pins the user can implement simultaneous power-supply sequencing by connecting the capacitor to the ssx pin, shown in figure 27 . using equation 4 and equation 5 , the capacitors can be calculated. (5) css1 css2 css3 vout1 vout2 vout3 = = en1 en2 en3 ss1 ss2 ss3 css en vout2 1.2 v vout1 1.5 v vout3 = 2.5 v en threshold = 1.2 v 31 32 1 24 8 17 ss ss c 0.6 v t = 15.6 a css(nf) vref( tss(m v) iss a s) ( ) m =
18 TPS65263-1Q1 slvsdy9 ? march 2017 www.ti.com product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 27. simultaneous startup sequence using ssx pins 7.3.4 power-up sequencing the TPS65263-1Q1 has a dedicated enable pin and soft-start pin for each converter. the converter enable pins are biased by a current source that allows for easy sequencing by the addition of an external capacitor. disabling the converter with an active pulldown transistor on the enx pin allows for predictable power-down timing operation. figure 28 shows the timing diagram of a typical buck power-up sequence with connecting a capacitor at the enx pin. a typical 1.4- a current is charging the enx pin from input supply. when the enx pin voltage rises to typical 0.4 v, the internal v7v ldo turns on. a 3.9- a pullup current is sourcing enx. after the enx pin voltage reaches the enx enabling threshold, a 3.0- a hysteresis current sources to the pin to improve noise sensitivity. the internal soft-start comparator compares the ss pin voltage to 1.2 v. when the ss pin voltage ramps up to 1.2 v, pgood monitor is enabled. after pgood deglitch time, pgood is deasserted. the ss pin voltage is eventually clamped around 2.1 v. en1 en2 en3 ss1 ss2 ss3 css1 vout2 1.2 v vout1 1.5 v vout3 = 2.5 v 31 32 1 24 8 17 css2 css3 en en threshold = 1.2 v ss ss c 3 0.6 v t = 5.2 a
19 TPS65263-1Q1 www.ti.com slvsdy9 ? march 2017 product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 28. startup power sequence 7.3.5 v7v low-dropout regulator and bootstrap power for the high-side and low-side mosfet drivers and most other internal circuitry is derived from the v7v pin. the internal built-in low-dropout linear regulator (ldo) supplies 6.3 v (typical) from vin to v7v. the user should connect a 1- f ceramic capacitor from v7v pin to power ground. if the input voltage, vin, decreases to the uvlo threshold voltage, the uvlo comparator detects the v7v pin voltage and forces the converter off. each high-side mosfet driver is biased from the floating bootstrap capacitor, cb, shown in figure 29 , which is normally recharged during each cycle through an internal low-side mosfet or the body diode of a low-side mosfet when the high-side mosfet turns off. the boot capacitor is charged when the bst pin voltage is less than vin and bst-lx voltage is below regulation. ti recommends a 47-nf ceramic capacitor. ti recommends a ceramic capacitor with an x7r or x5r grade dielectric with a voltage rating of 10 v or higher because of the stable characteristics over temperature and voltage. each low-side mosfet driver is powered from the v7v pin directly. to improve dropout, the device is designed to operate at 100% duty cycle as long as the bst to lx pin voltage is greater than the bst-lx uvlo threshold, which is typically 2.1 v. when the voltage between bst and lx drops below the bst-lx uvlo threshold, the high-side mosfet is turned off and the low-side mosfet is turned on allowing the boot capacitor to be recharged. en threshold enx rise time dictated by c en soft start rise time dictated by c ss enx voutx en threshold pgood pgood deglitch time t = c ss 1.2 v/5.2 a t = c en x (1.2 0.4) v/3.9 a t = c en x 0.4 v/1.4 a charge c en with 6.9 a pre-bias startup ssx 0.6 v 1.2 v about 2.1 v 1.2 v 0.4 v t = c ss 0.6 v/5.2 a vin v7v
20 TPS65263-1Q1 slvsdy9 ? march 2017 www.ti.com product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 29. v7v linear dropout regulator and bootstrap voltage diagram 7.3.6 out-of-phase operation to reduce input ripple current, the switch clock of buck1 is 180 out-of-phase from the clock of buck2 and buck3. this enables the system having less input current ripple to reduce input capacitors ? size, cost, and emi. ldo uvlo bias buck controller gate driver high-side mosfet low-side mosfet v7v vin pvinx bstx lxx cb cbias 1 uf (v bstx -v lxx ) +2.1 v nbootuv nbootuv pwm pwm nbootuv bootuv protection clk gate driver +
21 TPS65263-1Q1 www.ti.com slvsdy9 ? march 2017 product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.3.7 output overvoltage protection (ovp) the device incorporates an ovp circuit to minimize output voltage overshoot. when the output is overloaded, the error amplifier compares the actual output voltage to the internal reference voltage. if the fb pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier demands maximum output current. after the condition is removed, the regulator output rises and the error amplifier output transitions to the steady-state voltage. in some applications with small output capacitance, the load can respond faster than the error amplifier. this leads to the possibility of an output overshoot. each buck compares the fb pin voltage to the ovp threshold. if the fb pin voltage is greater than the ovp threshold, the high-side mosfet is turned off preventing current from flowing to the output and minimizing output overshoot. when the fb voltage drops lower than the ovp threshold, the high-side mosfet turns on at the next clock cycle. 7.3.8 psm the TPS65263-1Q1 can enter high-efficiency psm operation at light load current. to enable psm operation, set the voutx_com registers ? bit 1 to '1' through i 2 c interface. when a controller is enabled for psm operation, the peak inductor current is sensed and compared with 310-ma current typically. because the integrated current comparator catches the peak inductor current only, the average load current entering psm varies with the applications and external output filters. in psm, the sensed peak inductor current is clamped at 310 ma, shown in figure 30 . when a controller operates in psm, the inductor current is not allowed to reverse. the reverse current comparator turns off the low-side mosfet when the inductor current reaches 0, preventing it from reversing and going negative. due to the delay in the circuit and current comparator, tdly (typical 50 ns at vin = 12 v), the real peak inductor current threshold to turn off high-side power mosfet could shift higher depending on inductor inductance and input/output voltages. calculate the threshold of peak inductor current to turn off high-side power mosfet with equation 6 . (6) after the charge accumulated on the vout capacitor is more than loading need, the comp pin voltage drops to a low voltage driven by the error amplifier. there is an internal comparator at comp pin. if the comp voltage is < 0.35 v, the power stage stops switching to save power. figure 30. psm current comparator 7.3.9 slope compensation to prevent the subharmonic oscillations when the device operates at duty cycles greater than 50%, the TPS65263-1Q1 adds built-in slope compensation, which is a compensating ramp to the switch current signal. 7.3.10 overcurrent protection the device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side mosfet and low-side mosfet. il peak inductor peak current inductor current peak current sensing x1 current comparator delay: tdly turn off high-side power mosfet 310 ma + peak vin vout il 310 ma tdly l - = +
22 TPS65263-1Q1 slvsdy9 ? march 2017 www.ti.com product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.3.10.1 high-side mosfet overcurrent protection the device implements current mode control that uses the comp pin voltage to control the turn off of the high- side mosfet and the turn on of the low-side mosfet on a cycle-by-cycle basis. each cycle the switch current and the current reference generated by the comp pin voltage are compared, when the peak switch current intersects the current reference, the high-side switch is turned off. 7.3.10.2 low-side mosfet overcurrent protection while the low-side mosfet is turned on, its conduction current is monitored by the internal circuitry. during normal operation, the low-side mosfet sources current to the load. at the end of every clock cycle, the low-side mosfet sourcing current is compared to the internally set low-side sourcing current limit. if the low-side sourcing current is exceeded, the high-side mosfet is not turned on and the low-side mosfet stays on for the next cycle. the high-side mosfet is turned on again when the low-side current is below the low-side sourcing current limit at the start of a cycle. the low-side mosfet may also sink current from the load. if the low-side sinking current limit is exceeded, the low-side mosfet is turned off immediately for the rest of that clock cycle. in this scenario both mosfets are off until the start of the next cycle. furthermore, if an output overload condition (as measured by the comp pin voltage) has lasted for more than the hiccup wait time which is programmed for 256 switching cycles shown in figure 31 , the device shuts down and restarts after the hiccup time of 8192 cycles. the hiccup mode helps to reduce the device power dissipation under severe overcurrent condition. figure 31. overcurrent protection 7.3.11 power good the pgood pin is an open-drain output. when feedback voltage of each buck is between 95% (rising) and 105% (falling) of the internal voltage reference, the pgood pin pulldown is deasserted and the pin floats. ti recommends to use a pullup resistor between the values of 10 and 100 k ? to a voltage source that is 5.5 v or less. the pgood is in a defined state when the vin input voltage is greater than 1 v, but with reduced current sinking capability. the pgood achieves full current sinking capability after the vin input voltage is above uvlo threshold, which is 3.8 v. oc limiting (waiting) time 256 cycles hiccup time 8192 cycles soft start time t = css 0.6 v/5.2 a il inductor current ss ss pin voltage vout output voltage soft-start is reset after oc waiting time oc fault removed, soft-start, and output recovery 0.6 v about 2.1 v output over loading ocp peak inductor current threshold output hard short circuit
23 TPS65263-1Q1 www.ti.com slvsdy9 ? march 2017 product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated the pgood pin is pulled low when any feedback voltage of buck is lower than 92.5% (falling) or greater than 107.5% (rising) of the nominal internal reference voltage. also, when the pgood is pulled low, if the input voltage is undervoltage locked up, thermal shutdown is asserted, the en pin is pulled low or the converter is in soft-start period. the power-good indicator for each buck channel can be read back through i 2 c. the bits in sys_status[2:0] (address 0x06h) present the feedback voltage in regulation (logic 1) or not (logic 0) for buck1, buck2, and buck3 respectively 7.3.11.1 adjustable switching frequency the rosc pin can be used to set the switching frequency by connecting a resistor to gnd. the switching frequency of the device is adjustable from 200 khz to 2.3 mhz. to determine the rosc resistance for a given switching frequency, use equation 7 or the curve in figure 32 . to reduce the solution size, the user should set the switching frequency as high as possible, but consider tradeoffs of the supply efficiency and minimum controllable on-time. (7) figure 32. rosc vs switching frequency when an external clock applies to rosc pin, the internal pll has been implemented to allow internal clock synchronizing to an external clock between 200 and 2300 khz. to implement the clock synchronization feature, connect a square wave clock signal to the rosc pin with a duty cycle between 20% to 80%. the clock signal amplitude must transition lower than 0.4 v and higher than 2.0 v. the start of the switching cycle is synchronized to the falling edge of rosc pin. in applications where both resistor mode and synchronization mode are needed, the user can configure the device as shown in figure 33 . before an external clock is present, the device works in resistor mode and rosc resistor sets the switching frequency. when an external clock is present, the synchronization mode overrides the resistor mode. the first time the rosc pin is pulled above the rosc high threshold (2.0 v), the device switches from the resistor mode to the synchronization mode and the rosc pin becomes high impedance as the pll starts to lock onto the frequency of the external clock. ti does not recommend to switch from the synchronization mode back to the resistor mode because the internal switching frequency drops to 100 khz first before returning to the switching frequency set by rosc resistor. rosc (k : ) switching frequency (khz) 10 30 50 70 90 110 130 150 170 190 210 230 200 500 800 1100 1400 1700 2000 2300 d022 ( ) 0.966 osc ? khz 37254 r(k ) - = w
24 TPS65263-1Q1 slvsdy9 ? march 2017 www.ti.com product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 33. works with resistor mode and synchronization mode 7.3.12 thermal shutdown the internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds 160 c typically. the device reinitiates the power-up sequence when the junction temperature drops below 140 c typically. 7.4 device functional modes 7.4.1 serial interface description i 2 c is a 2-wire serial interface developed by nxp semiconductor (see i 2 c-bus specification , version 2.1, january 2000). the bus consists of a data line (sda) and a clock line (scl) with pullup structures. when the bus is idle, both sda and scl lines are pulled high. all the i 2 c-compatible devices connect to the i 2 c bus through open-drain i/o pins, sda and scl. a master device, usually a microcontroller or a digital signal processor, controls the bus. the master is responsible for generating the scl signal and device addresses. the master also generates specific conditions that indicate the start and stop of data transfer. a slave device receives and/or transmits data on the bus under control of the master device. the TPS65263-1Q1 device works as a slave and supports the following data transfer modes, as defined in the i 2 c-bus specification: standard mode (100 kbps) and fast mode (400 kbps). the interface adds flexibility to the power-supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. register contents remain intact as long as supply voltage remains above 3.8 v (typical). the data transfer protocol for standard and fast modes is exactly the same. therefore, they are referred to as f/s-mode in this document. the TPS65263-1Q1 device supports 7-bit addressing. 10-bit addressing and general call address are not supported. figure 34. i 2 c interface timing diagram sda scl start condition repeated start condition stop condition start condition tbuf thd,sta tsu,sto tsp tsu,sta tsu,dat tlow thd,sta thigh thd,dat tf tr rosc rosc ic mode selection
25 TPS65263-1Q1 www.ti.com slvsdy9 ? march 2017 product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated device functional modes (continued) 7.4.2 i 2 c update sequence the TPS65263-1Q1 requires a start condition, a valid i 2 c address, a register address byte, and a data byte for a single update. after the receipt of each byte, TPS65263-1Q1 device acknowledges by pulling the sda line low during the high period of a single clock pulse. a valid i 2 c address selects the TPS65263-1Q1. TPS65263-1Q1 performs an update on the falling edge of the lsb byte. when the TPS65263-1Q1 is in hardware shutdown (en1, en2, and en3 pin tied to ground) the device cannot be updated through the i 2 c interface. conversely, the i 2 c interface is fully functional during software shutdown (en1, en2, and en3 bit = 0). figure 35. i 2 c write data format figure 36. i 2 c read data format s 7-bit slave address 0 a register1 address a sr 1 7-bit slave address a data byte n p n: not acknowledge a: acknowledge s: start p: stop sr: repeated start system host chip s 7-bit slave address 0 a register address a data byte a p
26 TPS65263-1Q1 slvsdy9 ? march 2017 www.ti.com product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.5 register maps table 3. register addresses name bits address vout2_sel 8 0x01h vout1_com 8 0x03h vout2_com 8 0x04h vout3_com 8 0x05h sys_status 8 0x06h 7.5.1 vout2_sel: vout2 voltage selection register (address = 0x01h) figure 37. vout2_sel: vout2 voltage selection register 7 6 5 4 3 2 1 0 vout2_bit7 vout2_bit6 vout2_bit5 vout2_bit4 vout2_bit3 vout2_bit2 vout2_bit1 vout2_bit0 legend: r/w = read/write; r = read only; - n = value after reset table 4. vout2_sel: vout2 voltage selection register field descriptions bit field type reset description 7 vout2_bit7 r/w 0 ? go ? bit, must set 1 to enable i 2 c controlled vid voltages 6 vout2_bit6 r/w 0 128 voltage selections with 7-bits control voltage range: 0.68 to 1.95 v voltage step resolution: 10 mv 5 vout2_bit5 r/w 0 4 vout2_bit4 r/w 0 3 vout2_bit3 r/w 0 0x00h: vout2 = 0.68 v; 0x7fh: vout2 = 1.95 v 2 vout2_bit2 r/w 0 1 vout2_bit1 r/w 0 0 vout2_bit0 r/w 0 7.5.2 vout1_com: buck1 command register (offset = 0x03h) figure 38. vout1_com: buck1 command register 7 6 5 4 3 2 1 0 n/a mode1 nen1 legend: r/w = read/write; r = read only; - n = value after reset table 5. vout1_com: buck1 command register field descriptions bit field type reset description 7:2 n/a r/w 000000 not used 1 mode1 r/w 0 0: enable buck 1 pwm operation at light load; 1: forced buck 1 psm mode operation 0 nen1 r/w 0 0: enable buck1; 1: disable buck1
27 TPS65263-1Q1 www.ti.com slvsdy9 ? march 2017 product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.5.3 vout2_com: buck2 command register (offset = 0x04h) figure 39. vout2_com: buck2 command register 7 6 5 4 3 2 1 0 n/a sr3 sr2 sr1 n/a n/a mode2 nen2 legend: r/w = read/write; r = read only; - n = value after reset table 6. vout2_com: buck2 command register field descriptions bit field type reset description 7 n/a r/w 0 not used 6 sr3 r/w 0 vout2 vid voltage transition slew rate control. 5 sr2 r/w 0 000: 10 mv/cycle; 010: 10 mv/4 cycles; 100: 10 mv/16 cycles; 110: 10 mv/64 cycles; 001: 10 mv/2 cycles; 011: 10 mv/8 cycles; 101: 10 mv/32 cycles; 111: 10 mv/128 cycles 4 sr1 r/w 0 3 n/a r/w 0 not used 2 n/a r/w 0 not used 1 mode2 r/w 0 0: enable buck 2 pwm operation at light load; 1: forced buck 2 psm mode operation 0 nen2 r/w 0 0: enable buck2; 1: disable buck2 7.5.4 vout3_com: buck3 command register (offset = 0x05h) figure 40. vout3_com: buck3 command register 7 6 5 4 3 2 1 0 n/a mode3 nen3 legend: r/w = read/write; r = read only; - n = value after reset table 7. vout3_com: buck3 command register field descriptions bit field type reset description 7:2 n/a r/w 000000 not used 1 mode3 r/w 0 0: enable buck 3 pwm operation at light load; 1: forced buck 3 psm mode operation 0 nen3 r/w 0 0: enable buck3; 1: disable buck3
28 TPS65263-1Q1 slvsdy9 ? march 2017 www.ti.com product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 7.5.5 sys_status: system status register (offset = 0x06h) figure 41. sys_status: system status register 7 6 5 4 3 2 1 0 otp oc3 oc2 oc1 otw pgood3 pgood2 pgood1 legend: r/w = read/write; r = read only; - n = value after reset table 8. sys_status: system status register field descriptions bit field type reset description 7 otp r 0 1: die temperature over 160 c, which triggers over temperature protection; 0: die overtemperature protection is not triggered. 6 oc3 r 0 1: buck3 over current limiting and hiccup protection is triggered; 0: buck3 current not beyond the current limit. 5 oc2 r 0 1: buck2 overcurrent limiting and hiccup protection is triggered; 0: buck2 current not beyond the current limit. 4 oc1 r 0 1: buck1 overcurrent limiting and hiccup protection is triggered; 0: buck1 current not beyond the current limit. 3 otw r 0 1: die temperature over 125 c; 0: die temperature below 125 c. 2 pgood3 r 0 1: vout3 in power good monitor ? s range; 0: vout3 not in power good monitor ? s range. 1 pgood2 r 0 1: vout2 in power good monitor ? s range; 0: vout2 not in power good monitor ? s range. 0 pgood1 r 0 1: vout1 in power good monitor ? s range ; 0: vout1 not in power good monitor ? s range.
29 TPS65263-1Q1 www.ti.com slvsdy9 ? march 2017 product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the device is triple-synchronous step-down dc/dc converter with i 2 c interface. it is typically used to convert a higher dc voltage to lower dc voltages with continuous available output current of 3 a/2 a/2 a. 8.2 typical application the following design procedure can be used to select component values for the TPS65263-1Q1. this section presents a simplified discussion of the design process. figure 42. typical application schematic 8.2.1 design requirements this example details the design of triple-synchronous step-down converter. a few parameters must be known to start the design process. these parameters are typically determined at the system level. for this example, we start with the following known parameters: table 9. design parameters parameter value vout1 1.5 v iout1 3 a vout2 1.2 v iout2 2 a vout3 2.5 v iout3 2 a transient response 1-a load step 5% input voltage 12 v normal, 4 to 18 v output voltage ripple 1% switching frequency 500 khz 0.047 f c10 10 f c6 82 pf c8 0.01 f c21 3300 pf c18 22pf c14 0 r7 1 f c9 4.7 h l2 22 f c12 gnd gnd 10 f c5 0.047 f c20 0 r15 4.7 h l3 22 f c23 gnd 22 pf c26 gnd 4.7 h l1 22 f c3 22 f c2 gnd 0.047 f c1 0 r1 gnd en1 en2 en3 gnd 10.0 k r5 10.0 k r13 vout1 1.5 v 3 a vout2 1.2 v 2 a vout3 2.5 v 2 a vin 4 to 18 v gnd vfb1 vfb1 22 f c13 gnd vfb2 vfb2 vfb3 22 f c24 gnd vfb3 gnd 0.01 f c22 0.01 f c25 gnd 100 k r30 10.0 k r21 22 pf c11 3300 pf c19 22 pf c16 gnd gnd gnd gnd gnd gnd gnd gnd 10 f c7 sda scl v7v 1 f c4 gnd 15.0 k r6 10.0 k r14 31.6 k r22 100pf c17 2200 pf c15 10.0 k r12 10.0 k r10 10.0 k r8 v7v 88.7 k r23 vin vout1 vout2 vout3 (vout2 0.68 to 1.95 v via i c) 2 pvin1 28 comp2 7 fb2 6 en2 32 bst2 9 lx2 10 pgnd2 11 sda 2 scl 3 pgnd3 14 lx3 15 bst3 16 en3 1 fb3 19 agnd 4 v7v 30 comp1 23 ss1 24 fb1 22 en1 31 bst1 25 lx1 26 pgnd1 27 vin 29 comp3 18 vout2 5 pad pvin2 12 pvin3 13 rosc 21 pgood 20 ss2 8 ss3 17 u? tps652631q copyright ? 2017, texas instruments incorporated
30 TPS65263-1Q1 slvsdy9 ? march 2017 www.ti.com product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.2.2 detailed design procedure 8.2.2.1 output inductor selection to calculate the value of the output inductor, use equation 8 . lir is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. the inductor ripple current is filtered by the output capacitor. therefore, choosing high inductor ripple currents impact the selection of the output capacitor because the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. in general, the inductor ripple value is at the discretion of the designer; however, lir is normally from 0.1 to 0.3 for the majority of applications. (8) for the output filter inductor, it is important that the rms current and saturation current ratings not be exceeded. calculate the rms and peak inductor current from equation 10 and equation 11 . (9) (10) (11) the current flowing through the inductor is the inductor ripple current plus the output current. during power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. in transient conditions, the inductor current can increase up to the switch current limit of the device. for this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current. 8.2.2.2 output capacitor selection the three primary considerations for selecting the value of the output capacitor are: ? output capacitor determines the modulator pole ? output voltage ripple ? how the regulator responds to a large change in load current the output capacitance must be selected based on the most stringent of these three criteria. the desired response to a large change in the load current is the first criterion. the output capacitor needs to supply the load with current when the regulator cannot. this situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. the regulator is also temporarily not able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from no load to full load. the regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. the output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. the output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. equation 12 shows the minimum output capacitance necessary to accomplish this. where ? iout is the change in output current ? ? sw is the regulators switching frequency ? vout is the allowable change in the output voltage (12) ripple lpeak out i i i 2 = + ( ) 2 out inmax out inmax sw 2 lrms o v v v v l ? i i 12 ? ? - ? ? ? = + inmax out out ripple inmax sw v v v i l v ? - = inmax out out o inmax sw v v v l i lir v ? - = out o sw out 2 i c ? v d = d
31 TPS65263-1Q1 www.ti.com slvsdy9 ? march 2017 product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated equation 13 calculates the minimum output capacitance needed to meet the output voltage ripple specification. where ? ? sw is the switching frequency ? v oripple is the maximum allowable output voltage ripple ? i oripple is the inductor ripple current (13) equation 14 calculates the maximum esr an output capacitor can have to meet the output voltage ripple specification. (14) additional capacitance deratings for aging, temperature, and dc bias should be factored in, which increases this minimum value. capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. the user must specify an output capacitor that can support the inductor ripple current. some capacitor data sheets specify the root mean square (rms) value of the maximum ripple current. use equation 15 to calculate the rms ripple current the output capacitor needs to support. (15) 8.2.2.3 input capacitor selection the TPS65263-1Q1 requires a high-quality ceramic, type x5r or x7r, input decoupling capacitor of at least 10 f of effective capacitance on the pvin input voltage pins. in some applications, additional bulk capacitance may also be required for the pvin input. the effective capacitance includes any dc bias effects. the voltage rating of the input capacitor must be greater than the maximum input voltage. the capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS65263-1Q1. the input ripple current can be calculated using equation 16 . (16) the value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the capacitor. the capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. x5r and x7r ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance-to-volume ratio and are fairly stable over temperature. the output capacitor must also be selected with the dc bias taken into account. the capacitance value of a capacitor decreases as the dc bias across a capacitor increases. the input capacitance value determines the input ripple voltage of the regulator. use equation 17 to calculate the input voltage ripple. (17) 8.2.2.4 loop compensation the TPS65263-1Q1 incorporates a peak current mode control scheme. the error amplifier is a transconductance amplifier with a gain of 300 s. a typical type ii compensation circuit adequately delivers a phase margin between 40 and 90 . c b adds a high-frequency pole to attenuate high-frequency noise when needed. to calculate the external compensation components, follow these steps. 1. select switching frequency, ? sw , that is appropriate for application depending on l and c sizes, output ripple, emi, and so forth. switching frequency between 500 khz to 1 mhz gives best trade-off between performance and cost. to optimize efficiency, lower switching frequency is desired. 2. set up crossover frequency, ? c , which is typically between 1/5 and 1/20 of ? sw . 3. r c can be determined by: out max in in sw i 0.25 v c ? d = ( ) inmin out out inrms out inmin inmin v v v i i v v - = ( ) out inmax out corms inmax sw v v v i 12 v l ? - = oripple e sr oripple v r i < o oripple sw oripple 1 1 c v 8 ? i >
32 TPS65263-1Q1 slvsdy9 ? march 2017 www.ti.com product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated where ? g m_ea is the error amplifier gain (300 s). ? g m_ps is the power stage voltage to current conversion gain (7.4 a/v). (18) 4. calculate c c by placing a compensation zero at or before the dominant pole . (19) 5. optional c b can be used to cancel the zero from the esr associated with c o . (20) 6. type iii compensation can be implemented with the addition of one capacitor, c 1 . this allows for slightly higher loop bandwidths and higher phase margins. if used, calculate c 1 from equation 21 . (21) figure 43. dc/dc loop compensation esr b c r co c r = l c c r co c r = o l 1 ?p c r 2 = p ? ? ? ? c m ea m ps 2 ?c vo co r g vref g - - p = current sense i/v converter ref v 0.6 v l i esr r 1 r 2 r c r o c c c b c l r m _ ea g 300 us comp vfb ea 1 c m _ ps g 7.4 a / v lx fb vout + 1 1 c 1 c = ? 5 | s u
33 TPS65263-1Q1 www.ti.com slvsdy9 ? march 2017 product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 8.2.3 application curves iout = 3 a figure 44. buck1, soft-start iout = 2 a figure 45. buck2, soft-start iout = 2 a figure 46. buck3, soft-start iout = 3 a figure 47. buck1, output voltage ripple iout = 2 a figure 48. buck2, output voltage ripple iout = 2 a figure 49. buck3, output voltage ripple
34 TPS65263-1Q1 slvsdy9 ? march 2017 www.ti.com product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 0.75 to 1.5 a sr = 0.25 a/ s figure 50. buck1, load transient 1.5 to 2.25 a sr = 0.25 a/ s figure 51. buck1, load transient 0.5 to 1.0 a sr = 0.25 a/ s figure 52. buck2, load transient 1.0 to 1.5 a sr = 0.25 a/ s figure 53. buck2, load transient 0.5 to 1.0 a sr = 0.25 a/ s figure 54. buck3, load transient 1.0 to 1.5 a sr = 0.25 a/ s figure 55. buck3, load transient
35 TPS65263-1Q1 www.ti.com slvsdy9 ? march 2017 product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 56. buck1, hiccup and recovery figure 57. buck2, hiccup and recovery figure 58. buck3, hiccup and recovery figure 59. pgood figure 60. vid2 from 00 to 7f, sr = 10 mv/cycle figure 61. vid2 from 7f to 00, sr = 10 mv/cycle
36 TPS65263-1Q1 slvsdy9 ? march 2017 www.ti.com product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated figure 62. 180 out-of-phase figure 63. synchronization with external clock figure 64. operation at vin drop to 2.5 v vin = 12 v, vout1 = 1.5 v/3 a, vout2 = 1.2 v/2 a, vout3 = 2.5 v/2 a, t a = 26.8 c evm condition 4 layers, 75 mm 75 mm figure 65. thermal signature of TPS65263-1Q1evm operating
37 TPS65263-1Q1 www.ti.com slvsdy9 ? march 2017 product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 9 power supply recommendations the devices are designed to operate from an input voltage supply range between 4 and 18 v. this input power supply should be well regulated. if the input supply is located more than a few inches from the TPS65263-1Q1 converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. an electrolytic capacitor with a value of 47 f is a typical choice. 10 layout 10.1 layout guidelines figure 66 shows the TPS65263-1Q1 on a 2-layer pcb. layout is a critical portion of good power-supply design. see figure 66 for a pcb layout example. the top contains the main power traces for pvin, vout, and lx. the top layer also has connections for the remaining pins of the TPS65263-1Q1 and a large top-side area filled with ground. the top-layer ground area should be connected to the bottom layer ground using vias at the input bypass capacitor, the output filter capacitor, and directly under the TPS65263-1Q1 device to provide a thermal path from the exposed thermal pad land to ground. the bottom layer acts as ground plane connecting analog ground and power ground. for operation at full rated load, the top-side ground area together with the bottom-side ground plane must provide adequate heat dissipating area. several signals paths conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies' performance. to help eliminate these problems, bypass the pvin pin to ground with a low-esr ceramic bypass capacitor with x5r or x7r dielectric. take care to minimize the loop area formed by the bypass capacitor connections, the pvin pins, and the ground connections. the vin pin must also be bypassed to ground using a low-esr ceramic capacitor with x5r or x7r dielectric. because the lx connection is the switching node, the output inductor should be located close to the lx pins, and the area of the pcb conductor minimized to prevent excessive capacitive coupling. the output filter capacitor ground should use the same power ground trace as the pvin input bypass capacitor. try to minimize this conductor length while maintaining adequate width. the small signal components should be grounded to the analog ground path. the fb and comp pins are sensitive to noise so the resistors and capacitors should be located as close as possible to the ic and routed with minimal lengths of trace. the additional external components can be placed approximately as shown.
38 TPS65263-1Q1 slvsdy9 ? march 2017 www.ti.com product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 10.2 layout example figure 66. pcb layout sda scl en3 agnd fb2 comp2 ss2 vout2 comp1 fb1 ss1 rosc fb3 comp3 ss3 pgood lx1 pgnd1 bst1 pvin1 v7v en1 en2 vin lx3 pgnd3 bst3 pvin3 pgnd2 lx2 bst2 pvin2 pvin vout2 vout3 vout1 pvin vin topside ground area 0.010-inch diameter thermal via to ground plane via to ground plane
39 TPS65263-1Q1 www.ti.com slvsdy9 ? march 2017 product folder links: TPS65263-1Q1 submit documentation feedback copyright ? 2017, texas instruments incorporated 11 device and documentation support 11.1 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.3 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 11.4 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 11-apr-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tps65263-1qrhbrq1 preview vqfn rhb 32 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 tps 263-1q tps65263-1qrhbtq1 preview vqfn rhb 32 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 tps 263-1q (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 11-apr-2017 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of TPS65263-1Q1 : ? automotive: tps65263-q1 note: qualified version definitions: ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects

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